Recently, the 2025 IEEE International Solid-State Circuits Conference (ISSCC) was held in San Francisco, USA. The paper titled “A 6.78-MHz Single-Stage Regulating Rectifier with Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131mW Output Power” was accepted by the conference. This work was led by Professor Yi Shi and Associate Professor Hao Qiu from the School of Electronic Science and Engineering at Nanjing University. This work is Nanjing University's first ISSCC paper and was invited to give a demo during the conference. The team was awarded the ISSCC Silkroad Award, an outstanding award for students from universities within IEEE Region 10.
Rectifiers have been widely used in industrial automation, consumer electronics, medical equipment, and other fields, providing stable power supply for multifunctional modules of systems. Given the varying voltage requirements of different functional modules (such as microcontrollers, sensors, actuators, etc.), multi-output rectification has become the mainstream design direction. Compared with the multi-stage architecture of single-output rectification followed by multi-output DC-DC conversion, the single-stage architecture can avoid issues such as low power conversion efficiency and slow response during large load transient. However, most of the single-stage multi-output rectifiers reported so far adopted a time-division multiplexing approach to charge different output voltages. This approach has several shortcomings such as low load power and high ripple voltage, which limit its applications.
To conquer these limitations, the team proposed a novel single-stage dual-output rectifier chip topology, which can charge multiple outputs simultaneously within a half cycle. This significantly increases the load power and suppresses ripple voltage. Moreover, the team proposed an operation mode called charge distribution mode, which can address the usual challenge for voltage regulation during large load transient at the low-voltage output. By adaptively optimizing the charge distribution among multiple outputs, this mode effectively broadens the range of rated output current and significantly enhances the stability and adaptability of the circuit.
Chip photo and its circuit diagram
The proposed chip was fabricated using the 0.18 μm CMOS process for verification. Test results indicate that, under steady-state conditions, it achieved a peak efficiency of 92.2 % and a peak load power of 131 mW. The dual output voltages were regulated at 3.3 V and 1.6 V, respectively, with the maximum ripple voltages as small as 50 mV and 75 mV. Under a large load transient (×15), the chip achieved high-speed response while avoiding cross interference between the dual outputs. The core performance indexes are the highest among all previous works.
Quanrong Zhuang, a Ph.D. student at the School of Electronic Science and Engineering, Nanjing University, is the first author of the paper. Associate Professor Hao Qiu and Professor Yi Shi are the co-corresponding authors. Dr. Xin Zhang from the IBM Thomas J. Watson Research Center provided guidance for this work. This work was financially supported by the National Natural Science Foundation of China (62341408, 62374082, T2221003), the National Natural Science Foundation of China for Excellent Young Scholars (Overseas), the Engineering Research Center of Opto-Electro Materials and Chip Techniques, Nanjing University, Nanjing 210023, and the Interdisciplinary Research Center for Future Intelligent Chips, Nanjing University, Suzhou 215163, China.
Recently, affiliated with Nanjing University, the team has successfully developed multiple analog chips, which were published in top journals and conferences in the field of integrated circuits.
Analog chips successfully developed by the team in recent years
The International Solid-State Circuits Conference (ISSCC) is the top conference in the field of integrated circuit, also known as the “Olympics of Chips”. Since its inception in 1953, ISSCC has been the premier venue for the introduction of the world’s most advanced solid-state circuit technologies. These include the world’s first integrated analog amplifier chip (Fairchild Semiconductor), the first 8-bit microprocessor chip (Intel), the first 32-bit microprocessor chip (Intel), the first 1GB memory DRAM chip (Samsung), and the first multi-core processor chip (Intel).
ISSCC：https://www.isscc.org/
Group website：https://vlsi.nju.edu.cn/
